Main.PapilioPro History

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>>lrindent round frame float:right width:400px<<
'''Contents'''
[[<<]]
[[#Overview|Overview]][[<<]]
[[#PProFPGA|Spartan 6 LX9 FPGA]][[<<]]
[[#PProPower|Power]][[<<]]
[[#PProUSB|Dual Channel USB]][[<<]]
[[#PProSdram|SDRAM]][[<<]]
[[#PProSPIFlash|SPI Flash]][[<<]]
[[#PProIO|I/O]][[<<]]
[[#PProOscillator|Oscillator]][[<<]]
[[#PProJTAG|JTAG]][[<<]]
[[#PProReset|Reset]][[<<]]
[[#PProUserLED|User LED]][[<<]]
[[#PProLinks|Links]][[<<]]
[[#PProLicense|License]][[<<]]
[[#Images|Images]][[<<]]
>><<

[[#Overview]]
!!Papilio Pro
>>round frame<<
The Papilio Pro is an Open Source FPGA development board based on the
Xilinx Spartan 6 LX FPGA.
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 64Mb SDRAM, and an efficient switching power supply.
>><<

>>round frame float:left width:400px bgcolor=#ffffff<<
%width=500%[[Attach:ppro.jpg|Attach:ppro.jpg]]
>><<
[[<<]]

*Spartan 6 LX9 FPGA %newwin%([[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Datasheet]])
*High efficiency LTC3419 Step Down Dual Voltage Regulator %newwin%([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|Datasheet]])
*Dual Channel FTDI FT2232 USB 2.0 Full Speed Interface %newwin%([[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|Datasheet]])
*64Mbit Micron MT48LC4M16 SDRAM %newwin%([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|Datasheet]])
*64Mbit Macronix MX25L6445 SPI Flash %newwin%([[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
*48 I/O pins arranged in a Papilio Wing form factor
*32Mhz Crystal Oscillator
[[<<]]
----
[[#PProFPGA]]
!!!Spartan 6 LX9 FPGA
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:fpga_callout.png
The Papilio Pro's %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Spartan 3:

'''Digital Signal Processing (DSP) Slices'''
->18 DSP48A1 Slices for DSP functions.
'''Clock Management Tile (CMT)'''
->The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not offer any Phase-Locked Loops (PLL). The Papilio Pro (Spartan 6) offers the more flexible CMT which provides both DCM's and PLL's!
%rframe text-align=center width=200px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]|'''FPGA Schematic'''
\\
\\

'''New I/O Standards'''
->The Papilio Pro (Spartan 6) has direct TMDS I/O support which means that DVI and HDMI interfaces can be implemented without any extra chips.
'''Multi-Boot Support'''
->You can load multiple bit files into the SPI Flash and setup the first bit file to select which one will be loaded. With some work we could make a ZPUino based bootloader that would have a VGA interface to choose which bit file to load.
'''BRAM Memory Blocks'''
->The Spartan 6 allows 18Kbit BRAM blocks to be split into two 9Kbit BRAM blocks.
->There is more built in SRAM - there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Papilio Board
(:head bgcolor=#429ae0 :)18Kbit BRAM Blocks
(:head bgcolor=#429ae0 :)Max SRAM
(:head bgcolor=#429ae0 :)Usable SRAM
(:cellnr bgcolor=#c5d7dd:)Papilio Pro
(:cell bgcolor=#c5d7dd:)32
(:cell bgcolor=#c5d7dd:)576Kbit (72KByte)
(:cell bgcolor=#c5d7dd:)512Kbit (64KByte)
(:cellnr bgcolor=#7fc5e4:)Papilio One 500K
(:cell bgcolor=#7fc5e4:)20
(:cell bgcolor=#7fc5e4:)360Kbit (45KByte)
(:cell bgcolor=#7fc5e4:)320Kbit (40KByte)
(:cellnr bgcolor=#c5d7dd:)Papilio One 250K
(:cell bgcolor=#c5d7dd:)12
(:cell bgcolor=#c5d7dd:)216Kbit (27KByte)
(:cell bgcolor=#c5d7dd:)192Kbit (24KByte)
(:tableend:)

>>important<<
BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is possible to utilize the parity bits for data and gain access to all 18Kbit memory space.
>><<
[[<<]]
----
[[#PProPower]]
!!!Power
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:power-callout.png
%rframe text-align=center height=220px% [[Attach:power-schematic.png|Attach:power-schematic.png]]|'''Power Schematic'''

One of the big improvements with the Papilio Pro is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio Pro there is no detectable heat generated, even when the most demanding designs are running!
[[<<]]
----
[[#PProUSB]]
!!!Dual Channel USB
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:usb-callout.png
The Papilio Pro uses the same %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] dual channel USB chip that the Papilio One does.

*Channel A is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS).
[[<<]]

>>tip<<
The Papilio Pro includes a reset header (JP4) that can be populated with a jumper to hold the Spartan 6 FPGA in permanent reset mode. This frees up the JTAG Header to be used as an FT2232 JTAG/SPI/MPSSE Programmer.
>><<

%cframe text-align=center width=500% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
[[<<]]
----
[[#PProSdram]]
!!!SDRAM
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:sdram-callout.png
%rframe height=300px% [[Attach:sdram-schematic.png|Attach:sdram-schematic.png]]
The Papilio Pro includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge then interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.

\\

!!!SDRAM Designs
*[[http://hamsterworks.co.nz/mediawiki/index.php/SDRAM_Memory_Controller|Hamster's SDRAM Controller]]
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_hamster.vhd|Alvie's ZPUino SDRAM controller.]] (derived from Hamster's SDRAM controller).
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for Alvie's SDRAM controller.]]
*[[http://www.xilinx.com/support/documentation/application_notes/xapp394.pdf|XAPP 394 Interfacing Mobile SDRAM with CPLD's.]]
[[<<]]

>>tip<<
The ZPUino Soft Processor includes a SDRAM controller which gives your ZPUino sketches 8MByte of code space!
>><<
[[<<]]
----
[[#PProSPIFlash]]
!!!SPI Flash
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:flash-callout.png
%rframe width=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
[[<<]]

----
[[#PProIO]]
!!!I/O
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:io-callout.png
%rframe height=250px% [[Attach:io-schematic.png|Attach:io-schematic.png]]
The I/O of the Papilio Pro is backwards compatible with the Papilio One, all existing Papilio Wings and MegaWings work with the Papilio Pro.

The major difference between the Papilio Pro and Papilio One with respect to User I/O is the available voltage levels. The Papilio Pro sets all I/O voltage pins to 3.3V while the Papilio One can switch between 1.2V, 2.5V, and 3.3V. This was a seldom used feature that was dropped in the Papilio Pro for greater compatibility. Additionally, the Papilio Pro does not provide a 2.5V power rail, the 2.5V pin on the Wing Header is left unconnected. There are no Wings or MegaWings that use 2.5V power and there probably never will be... 3.3V seems to be the defacto standard for current peripherals.
[[<<]]

----
[[#PProOscillator]]
!!!Oscillator
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Manamgers (DCM)]] available for your designs.
[[<<]]

----
[[#PProJTAG]]
!!!JTAG
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:jtag-callout.png
%rframe width=200px% [[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]
The JTAG header on the Papilio Pro is provided for a couple different reasons:

'''Use a Xilinx Programming Cable'''
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].

'''Bypass the FPGA and use the FT2232 as a JTAG/SPI/MPSSE Programmer'''
->The Papilio Pro provides the JP4 pin header, jumping this header will hold the Spartan 6 FPGA in a reset state which frees up the JTAG pins to be controlled by the FT2232. OpenOCD, FlashRAM, and any other FT2232 based software should work directly with this method.

[[<<]]

----
[[#PProReset]]
!!!Reset
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:reset-callout.png
%rframe width=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]
Pressing the reset button will cause the Spartan 6 FPGA to do a hard reset and reload the first bit file from SPI Flash. This is a pretty drastic measure that will wipe out anything running on the FPGA. In most cases it is more desirable to utilize a user button to perform a reset within your design that just initializes all registers to zero.
[[<<]]

----
[[#PProUserLED]]
!!!User LED
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:led-callout.png
%rframe height=100px% [[Attach:led-schematic.png|Attach:led-schematic.png]]
The Papilio Pro provides one user LED that is connected directly to the Spartan 6 FPGA. It is not shared with any of the I/O pins and can be controlled directly from your VHDL or sketches.
[[<<]]

----
[[#PProLinks]]
!!!Links
'''Papilio Pro Design Files'''
->[[http://forum.gadgetfactory.net/index.php?/files/getdownload/34-papilio-pro-generic-ucf/|Papilio Pro Generic User Constraint File (UCF)]]
->[[https://github.com/GadgetFactory/Papilio-Pro/archive/master.zip|Papilio Pro EAGLE Design Files]]
->[[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=true|Papilio Pro Schematic (PDF)]]

'''Community Links'''
->[[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/papilio-pro/|Papilio Pro Project Showcase]]
->[[http://forum.gadgetfactory.net/index.php?/forum/102-papilio-pro-and-papilio-plus/|Papilio Pro Forum]]
->[[http://forum.gadgetfactory.net/index.php?/tags/downloads/papilio+pro/|Papilio Pro Downloads]]

[[<<]]

----
[[#PProLicense]]
!!!License
(:div style='text-align:center; background:#dddddd; border:1px solid #000000; width:100%; padding:5px;':)
%center%[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
Papilio Pro is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
Papilio Pro copyright Jack Gassett, Gadget Factory.
(:divend:)
[[<<]]

----
[[#Images]]
!!!Images
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:Papilio pro.png|Attach:Papilio pro.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilio pro2.png|Attach:papilio pro2.png]]
>>postit<<
%notetitle% Papilio Pro%%

Click the images for full size hi-resolution views of the Papilio Pro.
>><<
[[<<]]

%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
>>postit<<
%notetitle% Papilio Pro Schematic%%

Click the image to load a PDF version of the Papilio Pro Schematic
>><<
[[<<]]

%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro-assembly.png|Attach:ppro-assembly.png]]
>>postit<<
%notetitle% Assembly View%%

Click the image for a full size view of the boards part layout.
>><<
[[<<]]
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->[[http://forum.gadgetfactory.net/index.php?/tags/downloads/papilio+pro/|Papilio Pro Downloads]]
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'''Community Links'''
->[[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/papilio-pro/|Papilio Pro Project Showcase]]
->[[http://forum.gadgetfactory.net/index.php?/forum/102-papilio-pro-and-papilio-plus/|Papilio Pro Forum]]
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to:
'''Papilio Pro Design Files'''
->[[http://forum.gadgetfactory.net/index.php?/files/getdownload/34-papilio-pro-generic-ucf/|Papilio Pro Generic User Constraint File (UCF)]]
->[[https://github.com/GadgetFactory/Papilio-Pro/archive/master.zip|Papilio Pro EAGLE Design Files]]
->[[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=true|Papilio Pro Schematic (PDF)]]
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(:div style='text-align:center; background:#dddddd; border:1px solid #000000; width:100%; padding:5px;':)
%center%[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
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[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
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(:divend:)
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%lframe height=700 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
to:
%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
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|| border=1 width=90% align=center
||!Papilio Board ||!18Kbit BRAM Blocks ||!Max SRAM ||!Usable SRAM ||
|| '''Papilio Pro''' || '''32''' || '''576Kbit
(72KByte)''' || '''512Kbit (64KByte)''' ||
|| Papilio
One 500K || 20 || 360Kbit (45KByte) || 320Kbit (40KByte) ||
||
Papilio One 250K || 12 || 216Kbit (27KByte) || 192Kbit (24KByte) ||
to:
(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Papilio Board
(:head bgcolor=#429ae0 :)18Kbit BRAM Blocks
(:head bgcolor=#429ae0 :)Max SRAM
(:head bgcolor=#429ae0 :)Usable SRAM
(:cellnr bgcolor=#c5d7dd:)Papilio Pro
(:cell bgcolor=#c5d7dd:)32
(:cell bgcolor=#c5d7dd:)576Kbit
(72KByte)
(:cell bgcolor=#c5d7dd:)512Kbit (64KByte)
(:cellnr bgcolor=#7fc5e4:)Papilio
One 500K
(:cell bgcolor=#7fc5e4:)20
(:cell bgcolor=#7fc5e4:)360Kbit (45KByte)
(:cell bgcolor=#7fc5e4:)320Kbit (40KByte)
(:cellnr bgcolor=#c5d7dd:)Papilio One 250K
(:cell bgcolor=#c5d7dd:)12
(:cell bgcolor=#c5d7dd:)216Kbit (27KByte)
(:cell bgcolor=#c5d7dd:)192Kbit (24KByte)
(:tableend:)
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%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro1.jpg|Attach:ppro1.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro2.jpg|Attach:ppro2.jpg]]
to:
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:Papilio pro.png|Attach:Papilio pro.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilio pro2.png|Attach:papilio pro2.png]]
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Pressing the reset button will cause the Spartan 6 FPGA to do a hard reset and load the SPI bit file from SPI Flash. This is a pretty drastic measure that will wipe out anything running on the FPGA. In most cases it is more desirable to use a user button to perform a reset within our design that just initializes all registers to zero.
to:
Pressing the reset button will cause the Spartan 6 FPGA to do a hard reset and reload the first bit file from SPI Flash. This is a pretty drastic measure that will wipe out anything running on the FPGA. In most cases it is more desirable to utilize a user button to perform a reset within your design that just initializes all registers to zero.
Changed lines 113-114 from:
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for the SDRAM controller.]]
*[[http://www.xilinx.com/support/documentation/application_notes/xapp394.pdf|XAPP 394 Interfacing Moblle SDRAM with CPLD's.]]
to:
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for Alvie's SDRAM controller.]]
*[[http://www.xilinx.com/support/documentation/application_notes/xapp394.pdf|XAPP 394 Interfacing Mobile SDRAM with CPLD's.]]
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->The Spartan 6 allows 18Kbit BRAM blocks to be split into two independent 9Kbit BRAM blocks.
to:
->The Spartan 6 allows 18Kbit BRAM blocks to be split into two 9Kbit BRAM blocks.
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->The Spartan 6 allows 18Kbit BRAM blocks to be split into two independent 9Kbit BRAM blocks.
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->The Spartan 6 also allows 16Kbit BRAM blocks to be split into two independent 8Kbit BRAM blocks.
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->The Spartan 6 also allows 16Kbit BRAM blocks to be split into two independent 8Kbit BRAM blocks.
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%rframe height=300px% [[Attach:io-schematic.png|Attach:io-schematic.png]]
to:
%rframe height=250px% [[Attach:io-schematic.png|Attach:io-schematic.png]]
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%rframe height=300px% [[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]
to:
%rframe width=200px% [[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]
Changed lines 154-155 from:
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable.
The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].
to:
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].
Changed line 154 from:
If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable.
to:
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable.
Changed lines 158-159 from:
The Papilio Pro provides the JP4 pin header, jumping this header will hold the Spartan 6 FPGA in a reset state which frees up the JTAG pins to be controlled by the FT2232. OpenOCD, FlashRAM, and any other FT2232 based software should work directly with this method.
to:
->The Papilio Pro provides the JP4 pin header, jumping this header will hold the Spartan 6 FPGA in a reset state which frees up the JTAG pins to be controlled by the FT2232. OpenOCD, FlashRAM, and any other FT2232 based software should work directly with this method.
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%rframe height=300px% [[Attach:led-schematic.png|Attach:led-schematic.png]]
to:
%rframe height=100px% [[Attach:led-schematic.png|Attach:led-schematic.png]]
Changed lines 151-152 from:
to:
The JTAG header on the Papilio Pro is provided for a couple different reasons:

'''Use a Xilinx Programming Cable'''
If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable.
The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].

'''Bypass the FPGA and use the FT2232 as a JTAG/SPI/MPSSE Programmer'''
The Papilio Pro provides the JP4 pin header, jumping this header will hold the Spartan 6 FPGA in a reset state which frees up the JTAG pins to be controlled by the FT2232. OpenOCD, FlashRAM, and any other FT2232 based software should work directly with this method.
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Pressing the reset button will cause the Spartan 6 FPGA to do a hard reset and load the SPI bit file from SPI Flash. This is a pretty drastic measure that will wipe out anything running on the FPGA. In most cases it is more desirable to use a user button to perform a reset within our design that just initializes all registers to zero.
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The Papilio Pro provides one user LED that is connected directly to the Spartan 6 FPGA. It is not shared with any of the I/O pins and can be controlled directly from your VHDL or sketches.
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Papilio Pro is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
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Papilio Pro is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
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[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
Papilio Pro is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].

Papilio Pro copyright Jack Gassett, Gadget Factory.
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>>round frame<<
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro.jpg|Attach:ppro.jpg]]
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>><<

>>round frame float:left width:400px
bgcolor=#ffffff<<
%width
=500%[[Attach:ppro.jpg|Attach:ppro.jpg]]
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The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files on SPI Flash. Or we save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
to:
The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
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The I/O of the Papilio Pro is backwards compatible with the Papilio One, all existing Papilio Wings and MegaWings work with the Papilio Pro.

The major difference between the Papilio Pro and Papilio One with respect to User I/O is the available voltage levels. The Papilio Pro sets all I/O voltage pins to 3.3V while the Papilio One can switch between 1.2V, 2.5V, and 3.3V. This was a seldom used feature that was dropped in the Papilio Pro for greater compatibility. Additionally, the Papilio Pro does not provide a 2.5V power rail, the 2.5V pin on the Wing Header is left unconnected. There are no Wings or MegaWings that use 2.5V power and there probably never will be... 3.3V seems to be the defacto standard for current peripherals.
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The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Manamgers (DCM)]] available for your designs.
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The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files on SPI Flash. Or we save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
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*Digital Signal Processing (DSP) Slices
**18 DSP48A1 Slices for DSP functions.
*Clock Management Tile (CMT)
**The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not offer any Phase-Locked Loops (PLL). The Papilio Pro (Spartan 6) offers the more flexible CMT which provides both DCM's and PLL's!
to:
'''Digital Signal Processing (DSP) Slices'''
->
18 DSP48A1 Slices for DSP functions.
'''Clock Management Tile (CMT)'''
->
The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not offer any Phase-Locked Loops (PLL). The Papilio Pro (Spartan 6) offers the more flexible CMT which provides both DCM's and PLL's!
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*New I/O Standards
**The Papilio Pro (Spartan 6) has direct TMDS I/O support which means that DVI and HDMI interfaces can be implemented without any extra chips.
*Multi-Boot Support
**You can load multiple bit files into the SPI Flash and setup the first bit file to select which one will be loaded. With some work we could make a ZPUino based bootloader that would have a VGA interface to choose which bit file to load.
*There is more built in SRAM - there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!
to:
'''New I/O Standards'''
->
The Papilio Pro (Spartan 6) has direct TMDS I/O support which means that DVI and HDMI interfaces can be implemented without any extra chips.
'''Multi-Boot Support'''
->
You can load multiple bit files into the SPI Flash and setup the first bit file to select which one will be loaded. With some work we could make a ZPUino based bootloader that would have a VGA interface to choose which bit file to load.
'''BRAM Memory Blocks'''
->
There is more built in SRAM - there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!
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*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_hamster.vhd|Alvie's ZPUino SDRAM controller.]] (derived from Hamster's SDRAM controller). [[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for the SDRAM controller.]]
to:
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_hamster.vhd|Alvie's ZPUino SDRAM controller.]] (derived from Hamster's SDRAM controller).
*
[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for the SDRAM controller.]]
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%lframe height=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
to:
%lframe height=700 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
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[[<<]]
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
to:
%lframe height=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
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\\
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The Papilio Pro uses the same %newwin%([[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]]) dual channel USB chip that the Papilio One does.
to:
The Papilio Pro uses the same %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] dual channel USB chip that the Papilio One does.
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The Papilio Pro includes a 64Mbit Micron %newwin%([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]]) SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge then interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.
to:
The Papilio Pro includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge then interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.
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[[<<]]
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>>tip<<
The ZPUino Soft Processor includes a SDRAM controller which gives your ZPUino sketches 8MByte of code space!
>><<
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>>tip<<
The ZPUino Soft Processor includes a SDRAM controller which gives your ZPUino sketches 8MByte of code space!
>><<
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%cframe text-align=center% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
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%cframe text-align=center width=500% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
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%rframe text-align=center height=150px% [[Attach:power-schematic.png|Attach:power-schematic.png]]|'''Power Schematic'''
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%rframe text-align=center height=220px% [[Attach:power-schematic.png|Attach:power-schematic.png]]|'''Power Schematic'''
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%rframe text-align=center height=300px% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]
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*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS).
to:
*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS).
[[<<]]
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%cframe text-align=center% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
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%rframe width=400px% [[Attach:power-schematic.png|Attach:power-schematic.png]]
One of the big improvements with the Papilio Pro is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]])switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio Pro there is no detectable heat generated, even when the most demanding designs are running!
to:
%rframe text-align=center height=150px% [[Attach:power-schematic.png|Attach:power-schematic.png]]|'''Power Schematic'''
One
of the big improvements with the Papilio Pro is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio Pro there is no detectable heat generated, even when the most demanding designs are running!
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%rframe height=300px% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]
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%rframe text-align=center height=300px% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]
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%rframe width=200px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]
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%rframe text-align=center width=200px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]|'''FPGA Schematic'''
\\
\\
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|| border=1 width=70%
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|| border=1 width=90% align=center
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|| border=1 width=100%
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|| border=1 width=70%
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*Simplified power requirements, 2.5V it no longer required, just 1.2V and 3.3V.
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The Papilio Pro's %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Papilio One's Spartan 3:
to:
The Papilio Pro's %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Spartan 3:
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The %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Spartan 3 used in the Papilio One FPGA boards:
to:
The Papilio Pro's %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Papilio One's Spartan 3:
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%rframe width=200px
% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]
The %newwin%([[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]])
offers some exciting new features over the Spartan 3 used in the Papilio One FPGA boards:
to:
The %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Spartan 3 used in the Papilio One FPGA boards:
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%rframe width=200px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]
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%lframe width=300px bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:power-callout.png
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%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:power-callout.png
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%lframe width=450 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro.jpg|Attach:ppro.jpg]]
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro.jpg|Attach:ppro.jpg]]
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%lframe width=450 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro.jpg|Attach:ppro.jpg]]
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%lframe width=450 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro.jpg|Attach:ppro.jpg]]
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%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro3.jpg|Attach:ppro3.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro4.jpg|Attach:ppro4.jpg]]
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%rframe width=400px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]
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%rframe width=200px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]
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||!Papilio Board||!18Kbit BRAM Blocks||!Max SRAM||!Usable SRAM||
||'''Papilio Pro'''||'''32'''||'''576Kbit (72KByte)'''||'''512Kbit (64KByte)'''||
||Papilio One 500K||20||360Kbit (45KByte)||320Kbit (40KByte)||
||Papilio One 250K||12||216Kbit (27KByte)||192Kbit (24KByte)||
to:
||!Papilio Board ||!18Kbit BRAM Blocks ||!Max SRAM ||!Usable SRAM ||
|| '''Papilio Pro''' || '''32''' || '''576Kbit (72KByte)''' || '''512Kbit (64KByte)''' ||
|| Papilio One 500K || 20 || 360Kbit (45KByte) || 320Kbit (40KByte) ||
|| Papilio One 250K || 12 || 216Kbit (27KByte) || 192Kbit (24KByte) ||
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*There is more built in SRAM, in fact, there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!
!! border=1
||! Papilio Board||! 18Kbit BRAM Blocks||! Max SRAM||! Usable SRAM||
to:
*There is more built in SRAM - there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!

|| border=1 width=100%
||!Papilio Board||!18Kbit BRAM Blocks||!Max SRAM||!Usable SRAM||
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||Papilio Board||18Kbit BRAM Blocks||Max SRAM||Usable SRAM||
to:
!! border=1
||! Papilio Board||! 18Kbit BRAM Blocks||! Max SRAM||! Usable SRAM||
Changed lines 84-85 from:
*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS). The Papilio Pro also adds a reset header (JP4) that can be populated with a jumper to hold the Spartan 6 FPGA in permanent reset mode. This frees up the JTAG Header to be used as an FT2232 Programmer.
to:
*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS).
>>tip<<

The Papilio Pro includes a reset header (JP4) that can be populated with a jumper to hold the Spartan 6 FPGA in permanent reset mode. This frees up the JTAG Header to be used as an FT2232 JTAG/SPI/MPSSE Programmer.
>><<
Changed lines 96-105 from:
to:
The Papilio Pro includes a 64Mbit Micron %newwin%([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]]) SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge then interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.

>>tip<<
The ZPUino Soft Processor includes a SDRAM controller which gives your ZPUino sketches 8MByte of code space!
>><<

!!!SDRAM Designs
*[[http://hamsterworks.co.nz/mediawiki/index.php/SDRAM_Memory_Controller|Hamster's SDRAM Controller]]
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_hamster.vhd|Alvie's ZPUino SDRAM controller.]] (derived from Hamster's SDRAM controller). [[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for the SDRAM controller.]]
*[[http://www.xilinx.com/support/documentation/application_notes/xapp394.pdf|XAPP 394 Interfacing Moblle SDRAM with CPLD's.]]
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||'''Papilio Pro||'''32||'''576Kbit (72KByte)||'''512Kbit (64KByte)||
to:
||'''Papilio Pro'''||'''32'''||'''576Kbit (72KByte)'''||'''512Kbit (64KByte)'''||
Changed lines 82-84 from:
to:
The Papilio Pro uses the same %newwin%([[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]]) dual channel USB chip that the Papilio One does.
*Channel A is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS). The Papilio Pro also adds a reset header (JP4) that can be populated with a jumper to hold the Spartan 6 FPGA in permanent reset mode. This frees up the JTAG Header to be used as an FT2232 Programmer.
Changed line 48 from:
The Spartan 6 FPGA offers some exciting new features over the Spartan 3 used in the Papilio One FPGA boards:
to:
The %newwin%([[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]]) offers some exciting new features over the Spartan 3 used in the Papilio One FPGA boards:
Changed line 60 from:
||'''Papilio Pro||32||576Kbit (72KByte)||512Kbit (64KByte)'''||
to:
||'''Papilio Pro||'''32||'''576Kbit (72KByte)||'''512Kbit (64KByte)||
Changed line 74 from:
to:
One of the big improvements with the Papilio Pro is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]])switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio Pro there is no detectable heat generated, even when the most demanding designs are running!
Added lines 46-47:

%rframe width=400px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]
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*Simplified power requirements, 2.5V it no longer required, just 1.2V and 3.3V.
*Digital Signal Processing (DSP) Slices
**18 DSP48A1 Slices for DSP functions.
*Clock Management Tile (CMT)
**The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not offer any Phase-Locked Loops (PLL). The Papilio Pro (Spartan 6) offers the more flexible CMT which provides both DCM's and PLL's!
*New I/O Standards
**The Papilio Pro (Spartan 6) has direct TMDS I/O support which means that DVI and HDMI interfaces can be implemented without any extra chips.
*Multi-Boot Support
**You can load multiple bit files into the SPI Flash and setup the first bit file to select which one will be loaded. With some work we could make a ZPUino based bootloader that would have a VGA interface to choose which bit file to load.
Deleted lines 66-67:

%rframe width=400px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]
Added lines 46-54:
The Spartan 6 FPGA offers some exciting new features over the Spartan 3 used in the Papilio One FPGA boards:
*There is more built in SRAM, in fact, there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!
||Papilio Board||18Kbit BRAM Blocks||Max SRAM||Usable SRAM||
||'''Papilio Pro||32||576Kbit (72KByte)||512Kbit (64KByte)'''||
||Papilio One 500K||20||360Kbit (45KByte)||320Kbit (40KByte)||
||Papilio One 250K||12||216Kbit (27KByte)||192Kbit (24KByte)||
>>important<<
BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is possible to utilize the parity bits for data and gain access to all 18Kbit memory space.
>><<
Changed lines 34-37 from:
*High efficiency LTC3419 Step Down Dual Voltage Regulator ([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|Datasheet]])
*Dual Channel FTDI FT2232 USB 2.0 Full Speed Interface ([[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|Datasheet]])
*64Mbit Micron MT48LC4M16 SDRAM ([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|Datasheet]])
*64Mbit Macronix MX25L6445 SPI Flash ([[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
to:
*High efficiency LTC3419 Step Down Dual Voltage Regulator %newwin%([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|Datasheet]])
*Dual Channel FTDI FT2232 USB 2.0 Full Speed Interface %newwin%([[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|Datasheet]])
*64Mbit Micron MT48LC4M16 SDRAM %newwin%([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|Datasheet]])
*64Mbit Macronix MX25L6445 SPI Flash %newwin%([[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
Deleted line 39:
%%
Changed line 33 from:
*Spartan 6 LX9 FPGA ([[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Datasheet]])
to:
*Spartan 6 LX9 FPGA %newwin%([[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Datasheet]])
Added line 40:
%%
Changed lines 29-30 from:
to:
>><<
[[<<]]
Changed lines 21-22 from:
to:
>><<
Changed lines 29-30 from:
>><<
[[<<]]
to:
Deleted line 20:
>><<
Added lines 18-19:
[[#PProLinks|Links]][[<<]]
[[#PProLicense|License]][[<<]]
Changed lines 132-140 from:
[[#Images]]
!!!Images
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro1.jpg|Attach:ppro1.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro2.jpg|Attach:ppro2.jpg]]
>>postit<<
%notetitle% Papilio Pro%%

Click the images for full size hi-resolution views of the Papilio Pro.
>><<
to:
[[#PProLinks]]
!!!Links
Changed lines 137-139 from:
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro3.jpg|Attach:ppro3.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro4.jpg|Attach:ppro4.jpg]]
%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Wings/blob/master/BPM7004%20RetroCade%20Synth%20MegaWing/BPM7004_RetroCade_Synth_MegaWing.pdf?raw=true|Attach:ppro-schematic.png]]
to:
----
[[
#PProLicense]]
!!!License



[[<<]]

----
[[
#Images]]
!!!Images
%lframe width
=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro1.jpg|Attach:ppro1.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro2.jpg|Attach:ppro2.jpg]]
>>postit<<
%notetitle% Papilio Pro%%

Click the images for full size hi-resolution views of the Papilio Pro.
>><<
[[<<]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro3.jpg|Attach:ppro3.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro4.jpg|Attach:ppro4.jpg]]
%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee
|Attach:ppro-schematic.png]]
Changed lines 79-81 from:
%rframe height=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
to:
%rframe width=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
Changed lines 97-99 from:
%rframe height=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
to:
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
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%rframe height=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]
to:
%rframe width=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]
Changed line 32 from:
*High efficiency power supply designed around the LTC3419 Step Down Voltage Regulator ([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|Datasheet]])
to:
*High efficiency LTC3419 Step Down Dual Voltage Regulator ([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|Datasheet]])
Added lines 15-17:
[[#PProJTAG|JTAG]][[<<]]
[[#PProReset|Reset]][[<<]]
[[#PProUserLED|User LED]][[<<]]
Added lines 98-124:


[[<<]]

----
[[#PProJTAG]]
!!!JTAG
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:jtag-callout.png
%rframe height=300px% [[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]


[[<<]]

----
[[#PProReset]]
!!!Reset
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:reset-callout.png
%rframe height=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]


[[<<]]

----
[[#PProUserLED]]
!!!User LED
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:led-callout.png
%rframe height=300px% [[Attach:led-schematic.png|Attach:led-schematic.png]]
Changed lines 8-13 from:
[[#MegaWingMIDI|MegaWing MIDI]][[<<]]
[[#MegaWingSound|MegaWing Sound]][[<<]]
[[#MegaWingCharacterLCD|MegaWing Character LCD]][[<<]]
[[#MegaWingJoystick|MegaWing Joystick]][[<<]]
[[#MegaWingMicroSD|MegaWing MicroSD]][[<<]]
[[#MegaWingAnalogInput|MegaWing Analog Input]][[<<]]
to:
[[#PProFPGA|Spartan 6 LX9 FPGA]][[<<]]
[[#PProPower|Power]][[<<]]
[[#PProUSB|Dual Channel USB]][[<<]]
[[#PProSdram|SDRAM]][[<<]]
[[#PProSPIFlash|SPI Flash]][[<<]]
[[#PProIO|I/O]][[<<]]
[[#PProOscillator|Oscillator
]][[<<]]
Added line 30:
*64Mbit Micron MT48LC4M16 SDRAM ([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|Datasheet]])
Deleted line 31:
*64Mbit Micron MT48LC4M16 SDRAM ([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|Datasheet]])
Changed lines 37-62 from:
[[#MegaWingMIDI]]
!!!MegaWing MIDI
%lframe bgcolor=#c5d7dd border
='1px solid #429ae0'% Attach:midi_callout.png
The Midi section of the RetroCade MegaWing implements three MIDI jacks; MIDI IN, MIDI OUT, and MIDI THROUGH. MIDI In is used to connect MIDI instruments such as a MIDI Keyboard, MIDI control board, or MIDI sequencer to the RetroCade synth to send MIDI notes and Control Changes that tell the RetroCade what audio to output. MIDI Through is connected to the MIDI In port and passes everything that comes in over the MIDI In port back out so MIDI devices can be daisy chained together. MIDI Out can be used by the RetroCade to output MIDI data such as timing, change control's or notes.

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)MIDI TX
(:cell bgcolor=#c5d7dd:)MIDI Out Connector
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)C0
(:cellnr bgcolor=#7fc5e4:)MIDI RX
(:cell bgcolor=#7fc5e4:)MIDI In Connector
(:cell bgcolor=#7fc5e4:)Input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)C1
(:tableend:)

%rframe width=400px% [[Attach:midi_schematic.
png|Attach:midi_schematic.png]]
'''Technical Details'''
The RetroCade MIDI implementation is closely patterned after the recommended [[http://www.midi.org/techspecs/electrispec.php|MIDI circuit implementation]] provided by the MIDI Manufacturers Association. The only deviation from the recommended design is the use of a 3.3V power connection instead of 5V on the MIDI Out connector. This is necessary since the Papilio Pro uses 3.3V voltage levels instead of 5V levels.
to:
[[#PProFPGA]]
!!!Spartan 6 LX9 FPGA
%lframe bgcolor
=#c5d7dd border='1px solid #429ae0'% Attach:fpga_callout.png


%rframe width=400px% [[Attach:fpga_schematic
.png|Attach:fpga_schematic.png]]
Changed lines 46-50 from:
[[#MegaWingSound]]
!!!MegaWing Sound
%lframe bgcolor
=#c5d7dd border='1px solid #429ae0'% Attach:audio-callout.png
%rframe height=300px% [[Attach:audio-schematic.png|Attach:audio-schematic.png]]
Since sound is the most important aspect of the RetroCade Synth we have gone all out with the audio section. Two top of the line 1/4" [[http://www.mouser.com/Search/ProductDetail.aspx?R=NMJ6HCD2virtualkey56810000virtualkey550-22302|Neutrik audio jacks]] ([[http://www.neutrik.us/NMJ6HCD2|datasheet]]) are used to ensure solid high quality audio connections. A low pass filter combined with a high speed Delta-Sigma DAC, as outlined in [[http://www.xilinx.com/support/documentation/application_notes/xapp154.pdf|Xilinx App Note 154]], allows high quality audio output to be realized. The high speed of the FPGA clock allows the FPGA to do the heavy lifting of the Digital to Analog conversion.
to:
[[#PProPower]]
!!!Power
%lframe width
=300px bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:power-callout.png
%rframe width=400px% [[Attach:power-schematic.png|Attach:power-schematic.png]]
Deleted lines 52-82:

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)A1-Left
(:cell bgcolor=#c5d7dd:)Audio Jack 1 Left Channel
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)A1-Right
(:cell bgcolor=#7fc5e4:)Audio Jack 1 Right Channel
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)A2-Left
(:cell bgcolor=#c5d7dd:)Audio Jack 2 Left Channel
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)A2-Right
(:cell bgcolor=#7fc5e4:)Audio Jack 2 Right Channel
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:tableend:)

[[<<]]
Changed lines 54-67 from:
[[#MegaWingCharacterLCD]]
!!!MegaWing Character LCD
%lframe width=300px bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:lcd-callout.png
%rframe width=400px% [[Attach:lcd-schematic.png|Attach:lcd-schematic.png]]

\\
\\
\\
\\
\\
\\
\\

[[http://en.wikipedia.org/wiki/Hitachi_HD44780_LCD_controller|A 16x2 HD44780 compatible]] Character LCD is used to provide standalone control and feedback for the RetroCade. A standard backlight is provided for easy visibility in low light situations.
to:
[[#PProUSB]]
!!!Dual Channel USB
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:usb-callout.png
%rframe height=300px% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]
Deleted lines 61-109:
(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)LCD_Contrast
(:cell bgcolor=#c5d7dd:)Contrast adjustment
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)LCD_RS
(:cell bgcolor=#7fc5e4:)Register Select (RS). RS=0: Command, RS=1: Data
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)LCD_RW
(:cell bgcolor=#c5d7dd:)Read/Write (R/W). R/W=0: Write, R/W=1: Read
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)LCD_E
(:cell bgcolor=#7fc5e4:)Clock (Enable). Falling edge triggered
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:cellnr bgcolor=#c5d7dd:)LCD_DB4
(:cell bgcolor=#c5d7dd:)Bit 4
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)LCD_DB5
(:cell bgcolor=#7fc5e4:)Bit 5
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)LCD_DB6
(:cell bgcolor=#c5d7dd:)Bit 6
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)LCD_DB7
(:cell bgcolor=#7fc5e4:)Bit 7
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:tableend:)
[[<<]]
Changed lines 63-67 from:
[[#MegaWingJoystick]]
!!!MegaWing Joystick
%lframe
bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:joystick-callout.png
%rframe width=400px% [[Attach:joystick-schematic.png|Attach:joystick-schematic.png]]
A really slick [[http://www.ck-components.com/index.php?module=media&action=Display&cmpref=13333&lang=en&width=&height=&format=&alt=|TPA511GLFS digital joystick]] is included to make navigating menu's a snap. It provides four directions and select in a compact fingertip controlled form factor.
to:
[[#PProSdram]]
!!!SDRAM
%lframe
bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:sdram-callout.png
%rframe height=300px% [[Attach:sdram-schematic.png|Attach:sdram-schematic.png]]
Deleted lines 70-103:
(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)Joy_Left
(:cell bgcolor=#c5d7dd:)Joystick Left
(:cell bgcolor=#c5d7dd:)Input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)Joy_Down
(:cell bgcolor=#7fc5e4:)Joystick Down
(:cell bgcolor=#7fc5e4:)input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)Joy_Select
(:cell bgcolor=#c5d7dd:)Joystick Select
(:cell bgcolor=#c5d7dd:)input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)Joy_Right
(:cell bgcolor=#7fc5e4:)Joystick Right
(:cell bgcolor=#7fc5e4:)input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:cellnr bgcolor=#c5d7dd:)Joy_Up
(:cell bgcolor=#c5d7dd:)Joystick Up
(:cell bgcolor=#c5d7dd:)input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B3
(:tableend:)
[[<<]]
Changed lines 72-76 from:
[[#MegaWingMicroSD]]
!!!MegaWing MicroSD
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:uSD-callout.png
%rframe width=400px% [[Attach:uSD-schematic.png|Attach:uSD-schematic.png]]
The [[http://en.wikipedia.org/wiki/Microsd#microSD|MicroSD (Secure Digital)]] socket expands the RetroCade with GigaBytes worth of storage space for your audio and configuration files. SD Fat libraries over the standard SPI interface allows files to be copied directly from your computer's filesystem onto an uSD card that can be read by the RetroCade.
to:
[[#PProSPIFlash]]
!!!SPI Flash
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:flash-callout.png
%rframe height=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
Deleted lines 79-107:
(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)SD_DO
(:cell bgcolor=#c5d7dd:)Data Out [MISO]
(:cell bgcolor=#c5d7dd:)input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)SD_DI
(:cell bgcolor=#7fc5e4:)Data In [MOSI]
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)SD_SCK
(:cell bgcolor=#c5d7dd:)Clock [SCLK]
(:cell bgcolor=#c5d7dd:)output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)SD_nCS
(:cell bgcolor=#7fc5e4:)Card Select (Active Low)
(:cell bgcolor=#7fc5e4:)output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:tableend:)
[[<<]]
Changed lines 81-87 from:
[[#MegaWingAnalogInput]]
!!!MegaWing Analog Input
%lframe bgcolor
=#c5d7dd border='1px solid #429ae0'% Attach:adc-callout.png
%rframe width=400px% [[Attach:adc-schematic.png|Attach:adc-schematic.png]]
16 Analog inputs allow the RetroCade to be turned into a custom controller to implement your wildest [[http://www.controllerism.com/|controllerism]] ideas. The Analog header allows you to connect up to sixteen analog devices such as sliders, knobs, and analog joysticks. The header is even compatible with the Seeed Studio analog Grove devices when used with a [[http://www.seeedstudio.com/depot/electronic-brick-3-pin-to-grove-4-pin-converter-cable-5-pcs-pack-p-728.html?cPath=178_179|Grove to Brick adapter]]. Easily add [[http://www.seeedstudio.com/depot/grove-slide-potentiometer-p-1196.html?cPath=156_160|Grove Sliders]], [[http://www.seeedstudio.com/depot/grove-thumb-joystick-p-935.html?cPath=156_160|Grove Joysticks]], or any other [[http://www.seeedstudio.com/depot/index.php?main_page=advanced_search_result&search_in_description=1&keyword=grovefamily&inc_subcat=0&sort=20a&r_q=r&page=1&r_q=r|Analog Grove device]].

The 16 analog channels are implemented with two [[http://www.ti.com/lit/ds/symlink/adc088s102.pdf|ADC088S102CIMTX]] 8-bit, 8 Channel, SPI ADC's that are capable of sampling at speeds up to 1Msps.
to:
[[#PProIO]]
!!!I/O
%lframe bgcolor=#c5d7dd border
='1px solid #429ae0'% Attach:io-callout.png
%rframe height=300px% [[Attach:io-schematic.png|Attach:io-schematic.png]]
Deleted lines 88-136:
(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)ADC1_SCLK
(:cell bgcolor=#c5d7dd:)Clock [SCLK]
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)ADC1_DIN
(:cell bgcolor=#7fc5e4:)Data In [MOSI]
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)ADC1_DOUT
(:cell bgcolor=#c5d7dd:)Data Out [MISO]
(:cell bgcolor=#c5d7dd:)Input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)ADC1_nCS
(:cell bgcolor=#7fc5e4:)Card Select (Active Low)
(:cell bgcolor=#7fc5e4:)Input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:cellnr bgcolor=#c5d7dd:)ADC2_SCLK
(:cell bgcolor=#c5d7dd:)Clock [SCLK]
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)ADC2_DIN
(:cell bgcolor=#7fc5e4:)Data In [MOSI]
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)ADC2_DOUT
(:cell bgcolor=#c5d7dd:)Data Out [MISO]
(:cell bgcolor=#c5d7dd:)Input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)ADC2_nCS
(:cell bgcolor=#7fc5e4:)Card Select (Active Low)
(:cell bgcolor=#7fc5e4:)Input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:tableend:)
[[<<]]
Added lines 90-98:
[[#PProOscillator]]
!!!Oscillator
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe height=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]


[[<<]]

----
Changed lines 101-102 from:
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade1.jpg|Attach:rcade1.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade2.jpg|Attach:rcade2.jpg]]
to:
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro1.jpg|Attach:ppro1.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro2.jpg|Attach:ppro2.jpg]]
Changed lines 104-106 from:
%notetitle% RetroCade MegaWing%%

Click the images for full size hi-resolution views of the RetroCade MegaWing.
to:
%notetitle% Papilio Pro%%

Click the images for full size hi-resolution views of the Papilio Pro.
Changed lines 109-111 from:
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade3.jpg|Attach:rcade3.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade4.jpg|Attach:rcade4.jpg]]
%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Wings/blob/master/BPM7004%20RetroCade%20Synth%20MegaWing/BPM7004_RetroCade_Synth_MegaWing.pdf?raw=true|Attach:retrocade-schematic.png]]
to:
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro3.jpg|Attach:ppro3.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro4.jpg|Attach:ppro4.jpg]]
%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Wings/blob/master/BPM7004%20RetroCade%20Synth%20MegaWing/BPM7004_RetroCade_Synth_MegaWing.pdf?raw=true|Attach:ppro-schematic.png]]
Changed lines 113-115 from:
%notetitle% RetroCade MegaWing Schematic%%

Click the image to load a PDF version of the RetroCade MegaWing Schematic
to:
%notetitle% Papilio Pro Schematic%%

Click the image to load a PDF version of the Papilio Pro Schematic
Changed line 118 from:
%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:retrocade-assembly.png|Attach:retrocade-assembly.png]]
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro-assembly.png|Attach:ppro-assembly.png]]
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*48 I/O pins arranged in a Papilio Wing form factor.
to:
*48 I/O pins arranged in a Papilio Wing form factor
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%lframe width=450 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade2.jpg|Attach:rcade2.jpg]]
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%lframe width=450 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro.jpg|Attach:ppro.jpg]]
Changed lines 1-334 from:
(:include HardwareHeader:)
to:
(:notabledit:)
(:include HardwareHeader:)

>>lrindent round frame float:right width:270px<<
'''Contents'''
[[<<]]
[[#Overview|Overview]][[<<]]
[[#MegaWingMIDI|MegaWing MIDI]][[<<]]
[[#MegaWingSound|MegaWing Sound]][[<<]]
[[#MegaWingCharacterLCD|MegaWing Character LCD]][[<<]]
[[#MegaWingJoystick|MegaWing Joystick]][[<<]]
[[#MegaWingMicroSD|MegaWing MicroSD]][[<<]]
[[#MegaWingAnalogInput|MegaWing Analog Input]][[<<]]
[[#Images|Images]][[<<]]
>><<

[[#Overview]]
!!Papilio Pro
The Papilio Pro is an Open Source FPGA development board based on the
Xilinx Spartan 6 LX FPGA.
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 64Mb SDRAM, and an efficient switching power supply.
>><<
[[<<]]

%lframe width=450 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade2.jpg|Attach:rcade2.jpg]]
*Spartan 6 LX9 FPGA ([[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Datasheet]])
*High efficiency power supply designed around the LTC3419 Step Down Voltage Regulator ([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|Datasheet]])
*Dual Channel FTDI FT2232 USB 2.0 Full Speed Interface ([[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|Datasheet]])
*64Mbit Macronix MX25L6445 SPI Flash ([[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
*64Mbit Micron MT48LC4M16 SDRAM ([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|Datasheet]])
*48 I/O pins arranged in a Papilio Wing form factor.
*32Mhz Crystal Oscillator
[[<<]]

----
[[#MegaWingMIDI]]
!!!MegaWing MIDI
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:midi_callout.png
The Midi section of the RetroCade MegaWing implements three MIDI jacks; MIDI IN, MIDI OUT, and MIDI THROUGH. MIDI In is used to connect MIDI instruments such as a MIDI Keyboard, MIDI control board, or MIDI sequencer to the RetroCade synth to send MIDI notes and Control Changes that tell the RetroCade what audio to output. MIDI Through is connected to the MIDI In port and passes everything that comes in over the MIDI In port back out so MIDI devices can be daisy chained together. MIDI Out can be used by the RetroCade to output MIDI data such as timing, change control's or notes.

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)MIDI TX
(:cell bgcolor=#c5d7dd:)MIDI Out Connector
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)C0
(:cellnr bgcolor=#7fc5e4:)MIDI RX
(:cell bgcolor=#7fc5e4:)MIDI In Connector
(:cell bgcolor=#7fc5e4:)Input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)C1
(:tableend:)

%rframe width=400px% [[Attach:midi_schematic.png|Attach:midi_schematic.png]]
'''Technical Details'''
The RetroCade MIDI implementation is closely patterned after the recommended [[http://www.midi.org/techspecs/electrispec.php|MIDI circuit implementation]] provided by the MIDI Manufacturers Association. The only deviation from the recommended design is the use of a 3.3V power connection instead of 5V on the MIDI Out connector. This is necessary since the Papilio Pro uses 3.3V voltage levels instead of 5V levels.
[[<<]]

----
[[#MegaWingSound]]
!!!MegaWing Sound
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:audio-callout.png
%rframe height=300px% [[Attach:audio-schematic.png|Attach:audio-schematic.png]]
Since sound is the most important aspect of the RetroCade Synth we have gone all out with the audio section. Two top of the line 1/4" [[http://www.mouser.com/Search/ProductDetail.aspx?R=NMJ6HCD2virtualkey56810000virtualkey550-22302|Neutrik audio jacks]] ([[http://www.neutrik.us/NMJ6HCD2|datasheet]]) are used to ensure solid high quality audio connections. A low pass filter combined with a high speed Delta-Sigma DAC, as outlined in [[http://www.xilinx.com/support/documentation/application_notes/xapp154.pdf|Xilinx App Note 154]], allows high quality audio output to be realized. The high speed of the FPGA clock allows the FPGA to do the heavy lifting of the Digital to Analog conversion.
[[<<]]


(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)A1-Left
(:cell bgcolor=#c5d7dd:)Audio Jack 1 Left Channel
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)A1-Right
(:cell bgcolor=#7fc5e4:)Audio Jack 1 Right Channel
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)A2-Left
(:cell bgcolor=#c5d7dd:)Audio Jack 2 Left Channel
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)A2-Right
(:cell bgcolor=#7fc5e4:)Audio Jack 2 Right Channel
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:tableend:)

[[<<]]

----
[[#MegaWingCharacterLCD]]
!!!MegaWing Character LCD
%lframe width=300px bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:lcd-callout.png
%rframe width=400px% [[Attach:lcd-schematic.png|Attach:lcd-schematic.png]]

\\
\\
\\
\\
\\
\\
\\

[[http://en.wikipedia.org/wiki/Hitachi_HD44780_LCD_controller|A 16x2 HD44780 compatible]] Character LCD is used to provide standalone control and feedback for the RetroCade. A standard backlight is provided for easy visibility in low light situations.
[[<<]]

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)LCD_Contrast
(:cell bgcolor=#c5d7dd:)Contrast adjustment
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)LCD_RS
(:cell bgcolor=#7fc5e4:)Register Select (RS). RS=0: Command, RS=1: Data
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)LCD_RW
(:cell bgcolor=#c5d7dd:)Read/Write (R/W). R/W=0: Write, R/W=1: Read
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)LCD_E
(:cell bgcolor=#7fc5e4:)Clock (Enable). Falling edge triggered
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:cellnr bgcolor=#c5d7dd:)LCD_DB4
(:cell bgcolor=#c5d7dd:)Bit 4
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)LCD_DB5
(:cell bgcolor=#7fc5e4:)Bit 5
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)LCD_DB6
(:cell bgcolor=#c5d7dd:)Bit 6
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)LCD_DB7
(:cell bgcolor=#7fc5e4:)Bit 7
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:tableend:)
[[<<]]

----
[[#MegaWingJoystick]]
!!!MegaWing Joystick
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:joystick-callout.png
%rframe width=400px% [[Attach:joystick-schematic.png|Attach:joystick-schematic.png]]
A really slick [[http://www.ck-components.com/index.php?module=media&action=Display&cmpref=13333&lang=en&width=&height=&format=&alt=|TPA511GLFS digital joystick]] is included to make navigating menu's a snap. It provides four directions and select in a compact fingertip controlled form factor.
[[<<]]

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)Joy_Left
(:cell bgcolor=#c5d7dd:)Joystick Left
(:cell bgcolor=#c5d7dd:)Input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)Joy_Down
(:cell bgcolor=#7fc5e4:)Joystick Down
(:cell bgcolor=#7fc5e4:)input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)Joy_Select
(:cell bgcolor=#c5d7dd:)Joystick Select
(:cell bgcolor=#c5d7dd:)input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)Joy_Right
(:cell bgcolor=#7fc5e4:)Joystick Right
(:cell bgcolor=#7fc5e4:)input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:cellnr bgcolor=#c5d7dd:)Joy_Up
(:cell bgcolor=#c5d7dd:)Joystick Up
(:cell bgcolor=#c5d7dd:)input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B3
(:tableend:)
[[<<]]

----
[[#MegaWingMicroSD]]
!!!MegaWing MicroSD
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:uSD-callout.png
%rframe width=400px% [[Attach:uSD-schematic.png|Attach:uSD-schematic.png]]
The [[http://en.wikipedia.org/wiki/Microsd#microSD|MicroSD (Secure Digital)]] socket expands the RetroCade with GigaBytes worth of storage space for your audio and configuration files. SD Fat libraries over the standard SPI interface allows files to be copied directly from your computer's filesystem onto an uSD card that can be read by the RetroCade.
[[<<]]

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)SD_DO
(:cell bgcolor=#c5d7dd:)Data Out [MISO]
(:cell bgcolor=#c5d7dd:)input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)SD_DI
(:cell bgcolor=#7fc5e4:)Data In [MOSI]
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)SD_SCK
(:cell bgcolor=#c5d7dd:)Clock [SCLK]
(:cell bgcolor=#c5d7dd:)output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)SD_nCS
(:cell bgcolor=#7fc5e4:)Card Select (Active Low)
(:cell bgcolor=#7fc5e4:)output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:tableend:)
[[<<]]

----
[[#MegaWingAnalogInput]]
!!!MegaWing Analog Input
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:adc-callout.png
%rframe width=400px% [[Attach:adc-schematic.png|Attach:adc-schematic.png]]
16 Analog inputs allow the RetroCade to be turned into a custom controller to implement your wildest [[http://www.controllerism.com/|controllerism]] ideas. The Analog header allows you to connect up to sixteen analog devices such as sliders, knobs, and analog joysticks. The header is even compatible with the Seeed Studio analog Grove devices when used with a [[http://www.seeedstudio.com/depot/electronic-brick-3-pin-to-grove-4-pin-converter-cable-5-pcs-pack-p-728.html?cPath=178_179|Grove to Brick adapter]]. Easily add [[http://www.seeedstudio.com/depot/grove-slide-potentiometer-p-1196.html?cPath=156_160|Grove Sliders]], [[http://www.seeedstudio.com/depot/grove-thumb-joystick-p-935.html?cPath=156_160|Grove Joysticks]], or any other [[http://www.seeedstudio.com/depot/index.php?main_page=advanced_search_result&search_in_description=1&keyword=grovefamily&inc_subcat=0&sort=20a&r_q=r&page=1&r_q=r|Analog Grove device]].

The 16 analog channels are implemented with two [[http://www.ti.com/lit/ds/symlink/adc088s102.pdf|ADC088S102CIMTX]] 8-bit, 8 Channel, SPI ADC's that are capable of sampling at speeds up to 1Msps.
[[<<]]

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Name
(:head bgcolor=#429ae0 :)Function
(:head bgcolor=#429ae0 :)Direction|Arduino Pin
(:head bgcolor=#429ae0 :)Papilio Wing Pin
(:head bgcolor=#429ae0 :)FPGA Pin
(:cellnr bgcolor=#c5d7dd:)ADC1_SCLK
(:cell bgcolor=#c5d7dd:)Clock [SCLK]
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)ADC1_DIN
(:cell bgcolor=#7fc5e4:)Data In [MOSI]
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)ADC1_DOUT
(:cell bgcolor=#c5d7dd:)Data Out [MISO]
(:cell bgcolor=#c5d7dd:)Input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)ADC1_nCS
(:cell bgcolor=#7fc5e4:)Card Select (Active Low)
(:cell bgcolor=#7fc5e4:)Input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:cellnr bgcolor=#c5d7dd:)ADC2_SCLK
(:cell bgcolor=#c5d7dd:)Clock [SCLK]
(:cell bgcolor=#c5d7dd:)Output
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B1
(:cellnr bgcolor=#7fc5e4:)ADC2_DIN
(:cell bgcolor=#7fc5e4:)Data In [MOSI]
(:cell bgcolor=#7fc5e4:)Output
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B0
(:cellnr bgcolor=#c5d7dd:)ADC2_DOUT
(:cell bgcolor=#c5d7dd:)Data Out [MISO]
(:cell bgcolor=#c5d7dd:)Input
(:cell bgcolor=#c5d7dd:)?
(:cell bgcolor=#c5d7dd:)B2
(:cellnr bgcolor=#7fc5e4:)ADC2_nCS
(:cell bgcolor=#7fc5e4:)Card Select (Active Low)
(:cell bgcolor=#7fc5e4:)Input
(:cell bgcolor=#7fc5e4:)?
(:cell bgcolor=#7fc5e4:)B3
(:tableend:)
[[<<]]

----
[[#Images]]
!!!Images
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade1.jpg|Attach:rcade1.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade2.jpg|Attach:rcade2.jpg]]
>>postit<<
%notetitle% RetroCade MegaWing%%

Click the images for full size hi-resolution views of the RetroCade MegaWing.
>><<
[[<<]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade3.jpg|Attach:rcade3.jpg]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:rcade4.jpg|Attach:rcade4.jpg]]
%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Wings/blob/master/BPM7004%20RetroCade%20Synth%20MegaWing/BPM7004_RetroCade_Synth_MegaWing.pdf?raw=true|Attach:retrocade-schematic.png]]
>>postit<<
%notetitle% RetroCade MegaWing Schematic%%

Click the image to load a PDF version of the RetroCade MegaWing Schematic
>><<

%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:retrocade-assembly.png|Attach:retrocade-assembly.png]]
>>postit<<
%notetitle% Assembly View%%

Click the image for a full size view of the boards part layout.
>><<
[[<<]]
Changed line 1 from:
Ppro
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(:include HardwareHeader:)
Added line 1:
Ppro
  

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